CL=CL_0, BANK2=BANK2_0, COL8=COL8_0, BL=BL_0, COL=COL_0, PS=PS_0
SDRAM control register 0
| PS | Port Size 0 (PS_0): 8bit 1 (PS_1): 16bit |
| BL | Burst Length 0 (BL_0): 1 1 (BL_1): 2 2 (BL_2): 4 3 (BL_3): 8 4 (BL_4): 8 5 (BL_5): 8 6 (BL_6): 8 7 (BL_7): 8 |
| COL8 | Column 8 selection bit 0 (COL8_0): Column address bit number is decided by COL field. 1 (COL8_1): Column address bit number is 8. COL field is ignored. |
| COL | Column address bit number 0 (COL_0): 12 bit 1 (COL_1): 11 bit 2 (COL_2): 10 bit 3 (COL_3): 9 bit |
| CL | CAS Latency 0 (CL_0): 1 1 (CL_1): 1 2 (CL_2): 2 3 (CL_3): 3 |
| BANK2 | 2 Bank selection bit 0 (BANK2_0): SDRAM device has 4 banks. 1 (BANK2_1): SDRAM device has 2 banks. |